1. Field of the Invention
The present invention relates to a semiconductor light emitting device and a fabrication method of the semiconductor light emitting device. In particular, the present invention relates to a semiconductor light emitting device which can control of current and can optimize current density and in which a rise in luminosity is possible, and a fabrication method of the semiconductor light emitting device.
2. Description of the Related Art
In order to perform the rise in luminosity of an LED (Light Emitting Diode), a structure which forms a metallic reflective layer as a reflecting layer of light between a substrate and an active layer composed of an MQW (Multi-Quantum Well) layer is proposed. As a method of forming such the metallic reflective layer, for example, wafer bonding technology of a substrate of a light emitting diode layer is disclosed (for example, refer to the Patent Document 1 and Patent document 2).
On the other hand, an LED which decreases an invalidation light-emitting directly under an electrode relatively, and improves external quantum efficiency by processing pattern shape of surface electrode is also already disclosed (for example, refer to the Patent Document 3 and Patent document 4).
Generally, even if the LED enlarges current density, luminous efficiency does not become large infinitely. This phenomenon occurs according to the cause by which radiative recombination decreases, if temperature rises. Then, it is necessary to apply luminous efficiency into optimal current density for a chip size.
However, when applying high electric current, it is difficult to enlarge a chip size in respect of a size of a product. Moreover, although it is possible to distribute current and to apply optimal current density by connecting a small chip in parallel, the size of a package becomes large, and assembly mounting processes, such as die bonding and wire bonding, become complicated. Therefore, it was impossible to perform the control of the optimal current density in the conventional LED structure.                Patent document 1:        
Japanese Patent Application Laying-Open Publication No. Hei06-302857                Patent document 2:        
Specification of U.S. Pat. No. 5,376,580                Patent document 3:        
Japanese Patent Application Laying-Open Publication No. Hei05-145119                Patent document 4:        
Japanese Patent Application Laying-Open Publication No. Hei06-005921
Then, it is a subject to manufacture LED structure of obtaining optimal current density, by fixing a chip size by controlling conduction current, and by a method of not parallel-arranging small chips.